The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.
To achieve small geometry sizes and small pitch sizes, traditional semiconductor fabrication processes have used multiple photomasks to pattern a wafer. The use of multiple photomasks increases fabrication costs and prolongs fabrication time. In addition, alignment and overlay errors may become a greater concern, particularly as geometry sizes continue to shrink. Moreover, it may be difficult to form both a relatively large pattern and a relatively small pattern on a wafer at the same time. The large pattern may “disappear” or lose its shape under some existing fabrication techniques.
Therefore, while existing semiconductor fabrication methods to achieve small geometry sizes and small pitch sizes have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.